(1) Field of the Invention
The present invention relates to an evaluation and adjustment method of a semiconductor integrated circuit device, and particularly to an evaluation method of a System Large Scale Integration (LSI) which is designed based on Intellectual Property (IP).
(2) Description of the Related Art
It has been possible to manufacture a large scale integrated circuit onto one semiconductor chip by integrating complicated systems onto the semiconductor chip, following the dramatic increase in the number of transistors which can be integrated onto one semiconductor chip due to fine processing (for example, Patent Reference 1: Japanese Laid-Open Patent Application No. 2002-533738). Furthermore, the number of circuits, which do not contribute to normal operations of a Super Large Scale Integration (SLSI) such as test circuits and timing adjustment circuits, has been increased in order to test such large scale integrated circuit and to improve quality, and the wiring area has also been increased. With respect to circuits to be used to perform testing easier, wiring areas and the amount of power consumption have been reduced by sharing the circuits and controlling the circuits when they are not activated, and the like. However, in reality, a fundamental reduction in the number of circuits has not been realized.